MediaBench: a tool for evaluating and synthesizing multimedia and communications systems
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- Type
- article
- Published
- 1997-12-01
- Cited by
- 2,385
- References
- 31
- OpenAlex
- https://openalex.org/W2117285153
- Semantic Scholar
- https://api.semanticscholar.org/CorpusID:1339578
Keywords
Computer science, Very long instruction word, Suite, Compiler, SIMD
References
- Effective Compiler Support For Predicated Execution Using The Hyperblock
- Applied cryptography (2nd ed.): protocols, algorithms, and source code in C
- 3D Computer Graphics
- Computer Architecture: Pipelined and Parallel Processor Design
- System-level Synthesis Of Low-power Hard Real-time Systems
- Hardware-software interactions on Mpact
- Geust Editorial: Media processing: a new design target
- Dhrystone: a synthetic systems programming benchmark
- Highly concurrent scalar processing
- MicroUnity's MediaProcessor architecture
- Application-driven design of DSP architectures and compilers
- A VLIW architecture for a trace scheduling compiler
- Determining cost-effective multiple issue processor designs
- Custom-fit processors: letting applications define architectures
- Application-driven synthesis of core-based systems
- Trace Scheduling: A Technique for Global Microcode Compaction
- IMPACT: An Architectural Framework for Multiple-Instruction-Issue Processors Scott A. Mahlke Williani Y. Chen N ancy J. Worter Wen-niei W. Hwu
- IMPACT: an architectural framework for multiple-instruction-issue processors
- Applied cryptography: Protocols, algorithms, and source code in C
- Computer Organization & Design: The Hardware/Software Interface
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- Modeling the Global Critical Path in Concurrent Systems
- Performance Characterization of Data Mining Applications using MineBench
- Benchmarking modern multiprocessors
- Design and optimization of architectures for data intensive computing
- A New Approach to Thread Extraction for General-Purpose Programs
- Nanoprocessors: Configurable Hardware Accelerators for Embedded Systems
- Characterizing and Accelerating Bioinformatics Workloads on Modern Microarchitectures
- Mini-graph processing
- Profiling, Compilation, and HDL Generation within the hArtes Project
- Low-level estimation at high-levels of abstraction in system-level design
- On-chip adaptive components for balanced computing
- A Theory for Co-Scheduling Hardware and Software Pipelines in ASIPs and Embedded Processors
- Exploiting Application-Level Correctness for Low-Cost Fault Tolerance
- Context-based Branch Prediction for High-Performance and Low-Power Computing
- FSRAM: Flexible Sequential and Random Access Memory for Embedded Systems
- Power-Management Scheduling for Peak Power Minimization
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