FSRAM: Flexible Sequential and Random Access Memory for Embedded Systems
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Summary
A novel RAM architecture for embedded systems that allows both random-access and sequential access for reads and writes, using small “links” in each row that points to the next row to be prefetched is proposed.
- Type
- article
- Published
- 2004-01-01
- Cited by
- 2
- References
- 13
- OpenAlex
- https://openalex.org/W69507090
- Semantic Scholar
- https://api.semanticscholar.org/CorpusID:12489513
Keywords
Random access, Computer science, Overhead (engineering), Power consumption, Random access memory
References
- Hardware versus hybrid data prefetching in multimedia processors: a case study
- The SimpleScalar tool set, version 2.0
- Memory exploration for low power, embedded systems
- Push vs. pull: data movement for linked data structures
- Low-power sequential access memory design
- Architectural exploration and optimization of local memory in embedded systems
- Data cache sizing for embedded processor applications
- A comparison of hardware prefetching techniques for multimedia benchmarks
- Automatic data migration for reducing energy consumption in multi-bank memory systems
- Adaptive prefetching for multimedia applications in embedded systems
- MediaBench: a tool for evaluating and synthesizing multimedia and communications systems
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