IMPACT: An Architectural Framework for Multiple-Instruction-Issue Processors Scott A. Mahlke Williani Y. Chen N ancy J. Worter Wen-niei W. Hwu

Pohua P. Chang · 1991

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Type: article
Published: 1991-01-01
Cited by: 1
References: 8
OpenAlex: https://openalex.org/W2138480754
Semantic Scholar: https://api.semanticscholar.org/CorpusID:267802428

Keywords

Chen, Philosophy, Epistemology, Sociology, Computer science

References

MIPS R2000 RISC architectureGerry Kane — 1987
An Instruction Issuing Approach to Enhancing Performance in Multiple Functional Unit ProcessorsAcosta, Kjelstrup, Torng — 1986
Trace scheduling optimization in a retargetable microcode compilerMichael A. Howland, Robert A. Mueller, Philip Sweany — 1987
A VLIW architecture for a trace scheduling compilerRobert P. Colwell, Robert Nix, John J. O’Donnell — 1987
Trace Scheduling: A Technique for Global Microcode CompactionFisher — 1981
Tradeoffs in instruction format design for horizontal architecturesGurindar S. Sohi, Sriram Vajapeyam — 1989
Forward semantic: a compiler-assisted instruction fetch method for heavily pipelined processorsPo-Yung Chang, Wen mei Hwu — 1989
Limits on multiple instruction issueMichael D. Smith, M. Johnson, Mark Horowitz — 1989
Limits on multiple instruction issueMichael D. Smith, M. Johnson, Mark Horowitz — 1989
Code scheduling and register allocation in large basic blocksJames Goodman, Wei‐Chung Hsu — 2014

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MediaBench: a tool for evaluating and synthesizing multimedia and communications systemsChunho Lee, Miodrag Potkonjak, William H. Mangione-smith — 1997

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