On-chip adaptive components for balanced computing
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Summary
This dissertation aims to address the above issues in the context of reconfigurable architectures, by exploiting the possibility of using on-chip memory elements as computing units by proposing TriBank Register file architecture, a novel register file organization for wide-issue superscalar processors.
- Published
- 2003-01-01
- Cited by
- 0
- References
- 78
- Access
- Open access
- Semantic Scholar
- https://api.semanticscholar.org/CorpusID:58597791
References
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- Memory requirements for balanced computer architectures
- A Logic-in-Memory Computer
- Efficient Exploitation of Instruction-Level Parallelism for Superscalar Processors by the Conjugate Register File Scheme
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