NULL convention multiply and accumulate unit with conditional rounding, scaling, and saturation
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Summary
A number of alternative MAC algorithms are compared and contrasted in terms of throughput and area to determine which approach will yield the maximum throughput with the least area, and it was determined that two algorithms that meet these criteria well are the Modified Baugh-Wooley and Modified Booth2 algorithms.
- Type
- article
- Published
- 2002-06-01
- Cited by
- 32
- References
- 23
- Access
- Open access
- OpenAlex
- https://openalex.org/W2007067752
- Semantic Scholar
- https://api.semanticscholar.org/CorpusID:11440207
Keywords
Computer science, Parallel computing, Pipeline (software), Throughput, Correctness
References
- A DESIGN METHODOLOGY FOR SELF-TIME SYSTEMS
- A delay insensitive regular expression recognizer
- Self-timed rings and their application to division
- A low-power concurrent multiplier-accumulator using conditional evaluation
- Low-power multiplier design using delayed evaluation
- Computer arithmetic - algorithms and hardware designs
- Introduction to VLSI systems
- Synthesis of Asynchronous VLSI Circuits
- Delay-insensitive gate-level pipelining
- Switching theory in space technology
- Design and performance analysis of delay insensitive multi-ring structures
- Design of self-timed asynchronous Booth's multiplier
- Beware the isochronic fork
- NULL Convention Logic/sup TM/: a complete and consistent logic for asynchronous digital circuit synthesis
- Design of a delay-insensitive multiply-accumulate unit
- An Efficient Implementation of Boolean Functions as Self-Timed Circuits
- Gate and throughput optimizations for null convention self-timed digital circuits
- System Timing
- Design of delay insensitive circuits using multi-ring structures
- Computer arithmetic: Algorithms and hardware designs
Cited by
- Design of a NULL Convention Self-Timed Divider
- Propozycja metody mnożenia liczb ze znakiem
- Design and Characterization of NULL Convention Arithmetic Logic Units
- Signed multiplication technique by means of unsigned multiply instruction
- Optimization of NULL convention self-timed circuits
- Development of a large word-width high-speed asynchronous multiply and accumulate unit
- Communication pattern based methodology for performance analysis of termination detection schemes
- Further Speedup of a Large Word-Width High-Speed Asynchronous Multiply and Accumulate Unit
- Design And Synthesis Of Clockless Pipelines Based On Self-resetting Stage Logic
- Energy-Aware Data Movement In Non-Volatile Memory Hierarchies
- Low-Power Null Convention Logic Multiplier Design Based On Gate Diffusion Input Technique
- Asynchronous Floating-Point Adders and Communication Protocols: A Survey
- Speedup of a large word-width high-speed asynchronous Multiply and Accumulate unit
- Generic algorithms and NULL Convention Logic hardware implementation for unsigned and signed quad-rail multiplication
- Logically Determined Design
- Evaluation of Energy Efficient Processors with a Minimized Area Design and Low Voltage Operation
- Diverse Architectures for Low Energy High Throughput Computing
- Arithmetic Design Metrics on Area and Time efficiency of CMOS and Spintronic Devices
- Comparison of Architecture Processors Focusing on ALU and Floating Point Unit Designs
- Advances Power Efficiency of an Arithmetic Logic Unit through Size and Design
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