Advances Power Efficiency of an Arithmetic Logic Unit through Size and Design
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Summary
In this paper various Arithmetic Logic Unit (ALU) designs and their metrics are discussed and the ALU design using Probabilistic Domain Transformation is one of the most abstract ALU designs discussed.
- Published
- 2015-01-01
- Cited by
- 0
- References
- 10
- Semantic Scholar
- https://api.semanticscholar.org/CorpusID:210717723
References
- Design & analysis of 16 bit RISC processor using low power pipelining
- Energy and area analysis of a floating-point unit in 15nm CMOS process technology
- Design and evaluation of an ultra-area-efficient fault-tolerant QCA full adder
- NULL convention multiply and accumulate unit with conditional rounding, scaling, and saturation
- Energy-efficient multiplier-less discrete convolver through probabilistic domain transformation
- Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology
- 32 bit Multiplication and Division ALU Design Based on RISC Structure
- High throughput power-aware FIR filter design based on fine-grain pipelining multipliers and adders
- 64 bit green ALU design using clock gating technique on ultra scale FPGA
- Sub-500-ps 64-b ALUs in 0 . 18-m SOI / Bulk CMOS : Design and Scaling Trends
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