Design of a NULL Convention Self-Timed Divider
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Summary
An unsigned 8-bit ÷ 4-bit delay-insensitive iterative divider is developed using the NULL Convention Logic paradigm and yields an average cycle time of 75.92 ns with a transistor count of 4,721.
- Type
- article
- Published
- 2004-01-01
- Cited by
- 4
- References
- 20
- OpenAlex
- https://openalex.org/W32857083
- Semantic Scholar
- https://api.semanticscholar.org/CorpusID:1254330
Keywords
Null (SQL), Computer science, Mathematics, Data mining
References
- Design and Characterization of NULL Convention Arithmetic Logic Units
- Completion-Completeness for NULL Convention Digital Circuits Utilizing the Bit-Wise Completion Strategy
- Checking Delay-Insensitivity: 104 Gates and Beyond
- Computer arithmetic - algorithms and hardware designs
- Optimization of NULL convention self-timed circuits
- NULL convention multiply and accumulate unit with conditional rounding, scaling, and saturation
- A self-timed divider using a new fast and robust pipeline scheme
- Design and performance analysis of delay insensitive multi-ring structures
- A new asynchronous pipeline scheme: application to the design of a self-timed ring divider
- CMOS circuit design of threshold gates with hysteresis
- NULL Convention Logic/sup TM/: a complete and consistent logic for asynchronous digital circuit synthesis
- The design and implementation of an asynchronous radix-2 non-restoring 32-b/32-b ring divider
- Design and characterization of null convention self-timed multipliers
- Checking delay-insensitivity: 10/sup 4/ gates and beyond
- A multi-radix approach to asynchronous division
- A Zero-overhead Self-timed 160ns 54b CMOS Divider
- VLSI programming
- System Timing
- Asynchronous logics and application to information processing