SIS : A System for Sequential Circuit Synthesis

Keywords

Computer science, Sequential logic, Asynchronous communication, Asynchronous circuit, Combinational logic

References

• Decomposable searching problems and circuit optimization by retiming: two studies in general transformations of computational structuresJames B. Saxe — 1985
• Preserving Don't Care Conditions During RetimingEllen Sentovich, Robert K. Brayton — 1991
• A modified approach to two-level logic minimizationA.A. Malik, Robert K. Brayton, A. Richard Newton — 1988
• Performance-oriented technology mappingH.J. Touati, Cho W. Moon, Robert K. Brayton — 1990
• Advances in asynchronous circuit theory. Part I : gate and unbounded inertial delayJanusz Brzozowski, C.-J. Seger — 1990
• Don't care minimization of multi-level sequential logic networksBinshan Lin, H.J. Touati, A. Richard Newton — 1990
• Timing optimization of combinational logicK.J. Singh, A.R. Wang, Robert K. Brayton — 1988
• Logic synthesis for vlsi designRichard Rudell, Alberto Sangiovanni‐Vincentelli — 1989
• Synthesis of self-timed VLSI circuits from graph-theoretic specificationsT.-A. Chu — 1987
• Synthesis of hazard-free control circuits from asynchronous finite state machines specificationsTam-Anh Chu — 1994
• Multi-Level Logic Simplification Using Don't Cares and FiltersA. Saldanha, AChuan Wang, Robert K. Brayton — 1989
• Universal logic design algorithm and its application to the synthesis of two-level switching circuitsH.-J. Mathony — 1989
• MIS: A Multiple-Level Logic Optimization SystemRobert K. Brayton, Richard Rudell, Alberto Sangiovanni‐Vincentelli — 1987
• NOVA: State Assignment of Finite State Machines for Optimal Two-Level Logic ImplementationsTiziano Villa, Alberto Sangiovanni‐Vincentelli — 1989
• Minimization Over Boolean GraphsJ. P. Roth, Richard M. Karp — 1962
• Multi-level logic minimization using implicit don't caresK. Bartlett, Robert K. Brayton, Gary D. Hachtel — 1988
• Minimizing the Number of States in Incompletely Specified Sequential Switching FunctionsM. C. Paull, S.H. Unger — 1959
• Retiming and resynthesis: optimizing sequential networks with combinational techniquesSharad Malik, Ellen Sentovich, Robert K. Brayton — 1990
• Performance optimization of pipelined circuitsSharad Malik, K.J. Singh, Robert K. Brayton — 1990
• Improved logic synthesis algorithms for table look up architecturesRajeev Murgai, Narendra Shenoy, Robert K. Brayton — 1991

Cited by

• Synthesis and Verification of Digital Circuits using Functional Simulation and Boolean SatisfiabilityIgor L. Markov, Valeria Bertacco, Stephen M. Plaza — 2008
• An Integrated Technology Mapping EnvironmentAlan Mishchenko, Satrajit Chatterjee, Robert K. Brayton — 2005
• Digital Fingerprinting of Virtual ComponentsE. Charbon, I. Torunoglu — 1999
• Design Space Re-Engineering for Power Minimization in Modern Embedded SystemsYuan Lin — 2006
• Nanowire systems: technology and designPierre‐Emmanuel Gaillardon, Luca Amarù, Shashikanth Bobba — 2014
• Scalable Logic Synthesis using a Simple Circuit StructureAlan Mishchenko, Robert K. Brayton — 2006
• Restructuring multi-level networks by using function approximationsJordi Cortadella, Michael Kishinevsky, A. Mishchenko — 2003
• Regular Fabrics in Deep Sub-Micron Integrated-Circuit DesignFan Mo, Robert K. Brayton — 2004
• Thermal-driven Circuit Partitioning and Floorplanning with Power OptimizationKyoung-Keun Lee, Edward J. Paradise, Sung Kyu Lim — 2003
• Logic Complement, a New Method of Checking the Combinational CircuitsM. Gessel', Alexandre V. Morozov, Vladimir Sapozhnikov — 2003
• On-chip adaptive components for balanced computingR. Sangireddy, Arun Kumar Somani — 2003
• Automatic Process-Oriented Asynchronous Control Unit Generation from Control Data Flow GraphsEuiseok Kim, Jeong Gun Lee, Dong Ik Lee — 2001
• Switch-Level Test Generation of Competing Bridging Faults in the Presence of FeedbackKristian Wiklund, Tomas Magnusson, Peter Dahlgren — 1998
• Don't Care Computation in Minimizing Extended Finite State Machines with Presburger ArithmeticYunjian Jiang, Robert K. Brayton — 2002
• Logic Synthesis and Place-and-Route Environment for ORGAsMinoru Watanabe, Fuminori Kobayashi — 2006
• Algorithms for VLSI Circuit Optimization and GPU-Based ParallelizationYifang Liu — 2010
• High-Level Resource Binding and Allocation for Power and Performance OptimizationScott Cromar — 2009
• Enhanced SPFD Rewiring on Improving Rewiring AbilityJason Cong, Joey Y. Lin, Wangning Long — 2002
• Experimental Results for Self-Dual Multi-Output Combinational CircuitsV.V. Saposhnikov, Vl. Moshanin, V.V. Saposhnikov — 1999
• A Symbolic Inject-and-Evaluate Paradigm for Byzantine Fault DiagnosisShi‐Yu Huang — 2003

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• Synthesis and Optimization of Digital CircuitsG. Micheli — 1994
• Multilevel logic synthesisRobert K. Brayton, Gary D. Hachtel, Alberto Sangiovanni‐Vincentelli — 1990
• Logic Minimization Algorithms for VLSI SynthesisRobert K. Brayton, Gary D. Hachtel, Curtis T. McMullen — 1984
• An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designsJ. Cong, Yuzheng Ding — 1992