Multi-Level Logic Simplification Using Don't Cares and Filters

Keywords

Minification, Benchmark (surveying), Heuristic, Component (thermodynamics), Computer science

References

• A modified approach to two-level logic minimizationA.A. Malik, Robert K. Brayton, A. Richard Newton — 1988
• MIS: A Multiple-Level Logic Optimization SystemRobert K. Brayton, Richard Rudell, Alberto Sangiovanni‐Vincentelli — 1987
• Multi-level logic minimization using implicit don't caresK. Bartlett, Robert K. Brayton, Gary D. Hachtel — 1988
• Logic Minimization Algorithms for VLSI SynthesisRobert K. Brayton, Gary D. Hachtel, Curtis T. McMullen — 1984

Cited by

• Don't cares in multi-level network optimizationH. Savoj — 1992
• SIS : A System for Sequential Circuit SynthesisEllen Sentovich — 1992
• Logic minimization for factored formsA.A. Malik, Robert K. Brayton, Alberto Sangiovanni‐Vincentelli — 1989
• A cell-replicating approach to minicut-based circuit partitioningC. Kring, A. Richard Newton — 1991
• Consistency and observability invariance in multi-level logic synthesisPatrick C. McGeer, Robert K. Brayton — 1989
• A new logic minimization method for multiplexor-based FPGA synthesisRicardo Pezzuol Jacobi, A.-M. Trullemans — 1993
• Sequential equivalence checking of clock-gated circuitsYu-Yun Dai, Kei-Yong Khoo, Robert K. Brayton — 2015
• Finding Multiple Equivalence-Preserving Transformations in Combinational Circuits through Incremental-SATGianpiero Cabodi, Leandro Dipietro, Marco Murciano — 2010
• BooleDozer: Logic synthesis for ASICsLeon Stok, David S. Kung, Daniël Brand — 1996
• Sequential circuits for program analysisFadi A. Zaraket, Adnan Aziz, Sarfraz Khurshid — 2007
• SAT sweeping with local observability don't-caresQi Zhu, Nathan Kitchen, Andreas Kuehlmann — 2006
• New ATPG techniques for logic optimizationR. Jacoby, P. Moceyunas, H. Cho — 1989
• Circuit partitioning for logic synthesisS. Dey, F. Brglez, Gershon Kedem — 1991
• Retiming and resynthesis: optimizing sequential networks with combinational techniquesSharad Malik, Ellen Sentovich, Robert K. Brayton — 1990
• Multilevel logic synthesisRobert K. Brayton, Gary D. Hachtel, Alberto Sangiovanni‐Vincentelli — 1990
• Optimization of primitive gate networks using multiple output two-level minimizationA.A. Malik — 1992
• Logic Partitioning and Resynthesis for TestabilityK. De, P. Banerjee — 1991
• Improved logic synthesis algorithms for table look up architecturesRajeev Murgai, Narendra Shenoy, Robert K. Brayton — 1991
• On variable ordering of binary decision diagrams for the application of multi-level logic synthesisMasahiro Fujita, Yusuke Matsunaga, Taeko Kakuda — 1991
• Don't cares in synthesis: theoretical pitfalls and practical solutionsDaniël Brand, Reinaldo A. Bergamaschi, Leon Stok — 1998

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