Integrating Path and Timing Analysis Using Instruction-Level Simulation Techniques
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Summary
A new method that integrates path and timing analysis to address limitations of previously published methods for estimation of the worst-case execution time on contemporary processors with complex pipelines and multi-level memory hierarchies is presented.
- Published
- 1998-06-01
- Cited by
- 82
- References
- 15
- Semantic Scholar
- https://api.semanticscholar.org/CorpusID:7513183
References
- SimICS/Sun4m: A Virtual Workstation
- On the false path problem in hard real-time programs
- Complete worst-case execution time analysis of straight-line hard real-time programs
- Embra: fast and flexible machine simulation
- An accurate worst case timing analysis technique for RISC processors
- Bounding loop iterations for timing analysis
- Efficient worst case timing analysis of data caching
- Hardware/Software Architectures for Real-Time Caching
- Integrating the timing analysis of pipelining and instruction caching
- Timing analysis for data caches and set-associative caches
- Efficient microarchitecture modeling and path analysis for real-time software
- Worst-case execution time analysis for modern hardware architectures
- Automatic Accurate Time-Bound Analysis for High-Level Languages
- Deriving Annotations for Tight Calculation of Execution Time
Cited by
- Breaking Down Complexity for Reliable System-Level Timing Validation
- An Approach to Symbolic Worst-Case Execution Time Analysis
- Specification, modelling, verification and runtime analysis of real time systems
- Estimation de temps d'éxécution au pire cas par analyse statique et application aux systèmes d'exploitation temps réel
- Cache and Compiler Interaction : How to analyze, optimize and time cache behavior
- Symbolic representations in WCET analysis
- Certifying execution time in multicores
- Ensuring Integrity and Service Availability in a Web-Based Control Laboratory
- A Modular Tool Architecture for Worst-Case Execution Time Analysis
- Towards Industry-Strength Worst-Case Execution Time Analysis
- A Simple and Efficient Fully Automatic Worst-Case Execution Time Analysis for Model-Based Application Development
- A WCET Analysis Method for Pipelined Microprocessors with Cache Memories
- Worst-Case Execution Time Analysis of Disable Interrupt Regions in a Commercial Real-Time Operating System
- Integrated Control and Scheduling
- Predicting Time and Memory Demands of Object-Oriented Programs
- Supporting Timing Analysis by Automatic Bounding of Loop Iterations
- Improving WCET by optimizing worst-case paths
- Interactive Execution Time Predictions using Reference Attributed Grammars
- xBIL -- A Hardware Resource Oriented Binary Intermediate Language
- Static properties of commercial embedded real-time programs, and their implication for worst-case execution time analysis
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