Execution And Cache Performance Of A Decoupled Non-Blocking Multithreaded Architecture
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Summary
An evaluation of the execution performance and cache behavior of a new multithreaded architecture based on dataflow paradigm that eliminates complex hardware required for dynamic scheduling of instructions used in modern superscalar architectures.
- Type
- article
- Published
- 2000-01-01
- Cited by
- 0
- References
- 35
- OpenAlex
- https://openalex.org/W100256327
- Semantic Scholar
- https://api.semanticscholar.org/CorpusID:6220019
Keywords
Computer science, Blocking (statistics), Parallel computing, Cache, Operating system
References
- SISAL reference manual. Language version 2.0
- A Feasibility Study of a Memory Hierarchy in a Data Flow Environment
- Scheduled dataflow architecture : A synchronous execution paradigm for dataflow
- Computer Architecture: A Quantitative Approach
- A design study of the EARTH multiprocessor
- Decoupled access/execute computer architectures
- Super-threading: architectural and software mechanisms for optimizing parallel computation
- Missing the Memory Wall: The Case for Processor/Memory Integration
- A Chip-Multiprocessor Architecture with Speculative Multithreading
- Design of cache memories for dataflow architecture
- Design and performance evaluation of a multithreaded architecture
- The effectiveness of multiple hardware contexts
- The Superthreaded Processor Architecture
- A unified resource management and execution control mechanism for data flow machines
- Single instruction stream parallelism is greater than two
- A performance comparison of contemporary DRAM architectures
- Retrospective: Monsoon: an explicit token-store architecture
- Limits of instruction-level parallelism
- Limits of Control Flow on Parallelism
- Sparcle: an evolutionary processor design for large-scale multiprocessors
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