Limits of Control Flow on Parallelism
Explore this paper's citation graph
- Type
- article
- Published
- 1992-05-01
- Cited by
- 440
- References
- 21
- Access
- Open access
- OpenAlex
- https://openalex.org/W2133877928
- Semantic Scholar
- https://api.semanticscholar.org/CorpusID:13017754
Keywords
Computer science, Parallel computing, Instruction-level parallelism, Control flow, Parallelism (grammar)
References
- Superscalar microprocessor design
- Measuring the Parallelism Available for Very Long Instruction Word Architectures
- The Inhibition of Potential Parallelism by Conditional Jumps
- Reducing the cost of branches
- Critical issues regarding HPS, a high performance microarchitecture
- Highly concurrent scalar processing
- An efficient method of computing static single assignment form
- A VLIW architecture for a trace scheduling compiler
- Global instruction scheduling for superscalar machines
- SIMP (single Instruction Stream/multiple Instruction Pipelining): A Novel High-speed Single-processor Architecture
- Limits of instruction-level parallelism
- Trace Scheduling: A Technique for Global Microcode Compaction
- Comparing Software And Hardware Schemes For Reducing The Cost Of Branches
- Boosting beyond static scheduling in a superscalar processor
- Rechner-Architektur / Computer Architecture
- Limits on multiple instruction issue
- Implementation of precise interrupts in pipelined processors
- Limits on multiple instruction issue
Cited by
- Trace processors: exploiting hierarchy and speculation
- Synthesis of a Parallel Smith-Waterman Sequence Alignment Kernel into FPGA Hardware
- Evaluation of Alternative Data Speculation Approaches for Superscalar Processors
- Ordered multithreading: a novel technique for exploiting thread-level parallelism
- Exploiting thread-level parallelism on simultaneous multithreaded processors
- Adding Fast Interrupts to Superscalar Processors
- Incorporating guarded execution into existing instruction sets
- Loop transformations for clustered vliw architectures
- Using Timetags for Program Dependency Enforcement
- A finite state machine based format model of software pipelined loops with conditions
- A Directory-Based Scalable General-Purpose Shared-Memory Multiprocessor
- Levo: IPC in the 10's via Resource Flow Computing
- Instruction-level parallel processing: History, overview, and perspective
- Computing Along the Critical Path
- A Compiler-Based Speculative Execution Scheme for ILP Enhancement
- Execution And Cache Performance Of A Decoupled Non-Blocking Multithreaded Architecture
- Automatic Approach Towards Actor-Oriented Programming
- Principles of Instruction-Level Distributed Processing
- Single-program speculative multithreading (SPSM) architecture: compiler-assisted fine-grained multithreading
- Vliw processors: efficiently exploiting instruction level parallelism
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- Throughput Constrained Parallelism Reduction in Cyclo-static Dataflow Applications
- Limits of Parallelism on Thread-Level Speculative Parallel Processing Architecture