Single instruction stream parallelism is greater than two

Keywords

Microprocessor, Engineering, Library science, Electrical engineering, Computer science

References

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• Measuring the Parallelism Available for Very Long Instruction Word ArchitecturesJosé Carlos Nicolau, Fisher — 1984
• The Inhibition of Potential Parallelism by Conditional JumpsEdward M. Riseman, Caxton C. Foster — 1972
• Checkpoint Repair for High-Performance Out-of-Order Execution MachinesWen‐mei Hwu, Yale N. Patt — 1987
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• HPSm, a high performance restricted data flow architecture having minimal functionalityWen‐mei Hwu, Yale N. Patt — 1998
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• The Nonuniform Distribution of Instruction-Level and Machine Parallelism and Its Effect on PerformanceNorman P. Jouppi — 1989
• On the Number of Operations Simultaneously Executable in Fortran-Like Programs and Their Resulting SpeedupDavid J. Kuck, Yuki Muraoka, Shyh-Ching Chen — 1972
• Two-level adaptive training branch predictionTse-Yu Yeh, Yale N. Patt — 1991
• The hardware architecture of the CRISP microprocessorDavid R. Ditzel, Hubert R. McLellan, Alan D. Berenbaum — 1987
• Exploiting fine-grained parallelism through a combination of hardware and software techniquesStephen Melvin, Yale N. Patt — 1991
• HPS, a new microarchitecture: rationale and introductionYale N. Patt, Wen mei Hwu, Michael Shebanow — 1985
• Limits on multiple instruction issueMichael D. Smith, M. Johnson, Mark Horowitz — 1989
• Available instruction-level parallelism for superscalar and superpipelined machinesNorman P. Jouppi, D. W. Wall — 1989
• Limits on multiple instruction issueMichael D. Smith, M. Johnson, Mark Horowitz — 1989
• Available instruction-level parallelism for superscalar and superpipelined machinesNorman P. Jouppi, D. W. Wall — 1989

Cited by

• Evaluation of Alternative Data Speculation Approaches for Superscalar ProcessorsJosé María Faci González, Antonio González, Superscalar Processors — 1997
• Instruction-level parallel processing: History, overview, and perspectiveB. Ramakrishna Rau, Joseph A. Fisher — 2005
• Computing Along the Critical PathDean M. Tullsen, Brad Calder — 2002
• CRAIG: a practical framework for combining instruction scheduling and register assignmentThomas S. Brasier, Philip Sweany, Steven J. Beaty — 1995
• Execution And Cache Performance Of A Decoupled Non-Blocking Multithreaded ArchitectureKrishna M. Kavi, Roberto Giorgi, Joseph Arul — 2000
• Arquiteturas multi-tarefas simultâneas: SEMPRE: arquitetura SMT com capacidade de execução e escalonamento de processosRonaldo Augusto de Lara Gonçalves — 2000
• Single-program speculative multithreading (SPSM) architecture: compiler-assisted fine-grained multithreadingPradeep Dubey, Kevin O’Brien, Kathryn O’Brien — 1995
• Code Generation Schemas for Modulo Scheduled DO-Loops and WHILE-LoopsB. Ramakrishna Rau, Michael Schlansker, P. Tirumalai — 1992
• Systematic Computer Architecture PrototypingThomas M. Conte — 1992
• The Effects of Resource Limitations on Program ParallelismKevin B. Theobald, Guang R. Gao, Laurie Hendren — 1993
• Loop optimization techniques on multi-issue architecturesDan Richard Kaiser — 1995
• Software-oriented distributed shared cache management for chip multiprocessorsSanyenn Cho, Lei Jin — 2010
• Integrating Parallelizing Compilation Technology and Processor Architecture for Cost-Effective Concurrent multithreadingJenn Tsai, Zhenzhen Jiang, Zhiyuan Li — 1998
• Experimental Evaluation and Workload Characterization for High-Performance Computer ArchitecturesTarek A. El-Ghazawi — 1995
• Dynamic Scheduling in Multicore ProcessorsDemian Rosas Ham — 2012
• Achieving high levels of instruction-level parallelism with reduced hardware complexityMichael Schlansker, B. Ramakrishna Rau, Scott Mahlke — 1997
• Performance tradeoffs in multistreamed superscalar architecturesMaurício Serrano — 1994
• Scheduling a Superscalar Pipelined Processor Without Hardware InterlocksHeng-Yi Chao, Mary P. Harper — 1994
• Increasing superscalar performance through multistreamingWayne Yamamoto, Mario Nemirovsky — 1995
• A generic system simulator with novel on-chip cache and throughput models for gigascale integrationJ.C. Eble, Scott Wills, J.D. Meindl — 1998

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