Analysis of preemptively scheduled hard real-time systems
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Summary
This thesis presents a formal definition of the cache-related preemption delay, introduces the concept of definitely cached useful cache blocks, and presents new CRPD-aware response time analyses: ECB-Union and Multiset approaches.
- Type
- book
- Published
- 2013-03-19
- Cited by
- 12
- References
- 97
- Access
- Open access
- OpenAlex
- https://openalex.org/W54666225
- Semantic Scholar
- https://api.semanticscholar.org/CorpusID:9528124
Keywords
Computer science
References
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- Principles of Program Analysis
- Trace-Based Abstract Interpretation of Operational Semantics
- A Definition and Classification of Timing Anomalies
- Scheduling analysis of real-time systems with precise modeling of cache related preemption delay
- Instruction cache locking for multi-task real-time embedded systems
- Generic control flow reconstruction from assembly code
- Exact response-time analysis for fixed-priority preemption-threshold scheduling
- Sensitivity of cache replacement policies
Cited by
- A generic and compositional framework for multicore response time analysis
- Tight integration of cache, path and task-interference modeling for the analysis of hard real time systems
- Analysis of Write-back Caches under Fixed-priority Preemptive and Non-preemptive Scheduling
- Bridging Information Visualization with Machine Learning
- An extensible framework for multicore response time analysis
- Many-Core Timing Analysis of Real-Time Systems. (Analyse temporelle des systèmes temps-réels sur architectures pluri-coeurs)
- Response-time analysis for fixed-priority systems with a write-back cache
- Shared Cache Analysis Under Preemptive Scheduling
- Towards Analysing Cache-Related Preemption Delay in Non-Inclusive Cache Hierarchies
- LLVMTA: An LLVM-Based WCET Analysis Tool
- Mixed Criticality on Multicore/Manycore Platforms
- 20th International Workshop on Worst-Case Execution Time Analysis, WCET 2022, Modena, Italy, July 5, 2022