A mathematical approach towards hardware design
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Summary
This work focuses on streaming applications: i.e. applications that can be modeled as data-flow graphs that allow a designer to describe circuits in a more natural and concise way than possible with the language elements found in the traditional hardware description languages.
- Type
- article
- Published
- 2010-12-14
- Cited by
- 300
- References
- 24
- Access
- Open access
- OpenAlex
- https://openalex.org/W1490174819
- Semantic Scholar
- https://api.semanticscholar.org/CorpusID:505723
Keywords
Haskell, Computer science, VHDL, Compiler, Programming language
References
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- Constraint solving for high-level WCET analysis
- Microprocessor specification in Hawk
- The Worst Case Execution Time Tool Challenge 2006
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- muFP, a language for VLSI design
- Communication between nested loop programs via circular buffers in an embedded multiprocessor system
- Exercises in Architecture Specification Using CLaSH
- Lava: hardware design in Haskell
- The worst-case execution time tool challenge 2006
- Efficient Memoization for Dynamic Programming with Ad-Hoc Constraints
- Push-assisted migration of real-time tasks in multi-core processors
- Scratchpad Memory Management Techniques for Code in Embedded Systems without an MMU
- Scratchpad memories vs locked caches in hard real-time systems: a quantitative comparison
- C?aSH: Structural Descriptions of Synchronous Hardware Using Haskell
- HML, a novel hardware description language and its translation to VHDL
- Chronos: A timing analyzer for embedded software
- Scratchpad memories vs locked caches in hard real-time systems: a quantitative comparison
- The Worst Case Execution Time Tool Challenge 2006: The External Test
Cited by
- Analysis of preemptively scheduled hard real-time systems
- Architecture multi-coeurs et temps d'exécution au pire cas. (Multicore architectures and worst-case execution time)
- To a new hardware design methodology: A case study of the cochlea model
- Precision Timed Machines
- Testing a Timing Analysis tool : SWEET
- An Adaptive Property-Aware HW/SW Framework for DDDAS
- Identifying Relevant Parameters to Improve WCET Analysis
- Automatic Generation of Timing Models for Timing Analysis of High-Level Code.
- The Auspicious Couple: Symbolic Execution and WCET Analysis
- Extending WCET benchmark programs
- Improved precision in polyhedral analysis with wrapping
- Integrated Worst-Case Execution Time Estimation of Multicore Applications
- Deriving WCET Bounds by Abstract Execution
- Certifying execution time in multicores
- Simulation efficace d'architectures opérationnelles
- Loop Patterns in C Programs
- Proactive Energy-Aware Programming with PEEK
- PWCET: Power-Aware Worst Case Execution Time Analysis
- The use of automated search in deriving software testing strategies
- A probabilistically analysable cache implementation on FPGA
Related papers
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- Abstract interpretation
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