A High‐On/Off‐Ratio Floating‐Gate Memristor Array on a Flexible Substrate via CVD‐Grown Large‐Area 2D Layer Stacking
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Summary
A highly reliable memristor array using floating-gate memory operated by two terminals (source and drain) using van der Waals layered materials is demonstrated, opening a practical route for next-generation electronics with CVD-grownVan der Waal layered materials.
- Type
- article
- Published
- 2017-11-01
- Cited by
- 161
- References
- 27
- OpenAlex
- https://openalex.org/W28949418
- Semantic Scholar
- https://api.semanticscholar.org/CorpusID:41835332
Keywords
Political science
References
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Cited by
- Doping engineering and functionalization of two-dimensional metal chalcogenides.
- Very high open-circuit voltage in dual-gate graphene/silicon heterojunction solar cells
- Recent Advances in van der Waals Heterojunctions Based on Semiconducting Transition Metal Dichalcogenides
- Wafer-scale fabrication of microelectrode arrays on optically transparent polymer foils for the integration of flexible nanoscale devices
- Dendrite Integration Mimicked on Starch-Based Electrolyte-Gated Oxide Dendrite Transistors.
- 2D Transition Metal Dichalcogenide Thin Films Obtained by Chemical Gas Phase Deposition Techniques
- Neuromorphic MoS2 memtransistors fabricated by localised helium ion beam irradiation.
- Layer‐Dependent Dielectric Function of Wafer‐Scale 2D MoS2
- Two‐Terminal Multibit Optical Memory via van der Waals Heterostructure
- Nonvolatile Memories Based on Graphene and Related 2D Materials
- New Floating Gate Memory with Excellent Retention Characteristics
- Resistive switching behavior and mechanism in flexible TiO2@Cf memristor crossbars
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- Bridging Biological and Artificial Neural Networks with Emerging Neuromorphic Devices: Fundamentals, Progress, and Challenges
- A nanofluidic memristor based on ion concentration polarization.
- High on/off ratio black phosphorus based memristor with ultra-thin phosphorus oxide layer
- MoS2 Memtransistors Fabricated by Localized Helium Ion Beam Irradiation.
- Clean Interface Contact Using ZnO Interlayer for Low-Contact-Resistance MoS2 Transistors.
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