Minimized reversible synthesis of non-reversible quinary logic function
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- Type
- article
- Published
- 2009-12-01
- Cited by
- 2
- References
- 20
- OpenAlex
- https://openalex.org/W2537520392
- Semantic Scholar
- https://api.semanticscholar.org/CorpusID:14970821
Keywords
Quinary, Logic gate, Realization (probability), Minification, Logic synthesis
References
- Design of Reversible/Quantum Ternary Comparator Circuits
- Multiple-Valued Quantum Logic Synthesis
- A Transformation Based Algorithm for Ternary Reversible Logic Synthesis using Universally Controlled Ternary Gates
- Design of Reversible/Quantum Ternary Multiplexer and Demultiplexer
- A recursive method for synthesizing quantum/reversible quaternary parallel adder/subtractor with look-ahead carry
- Multivalued logic gates for quantum computation
- Quantum ternary parallel adder/subtractor with partially-look-ahead carry
- Synthesis of quaternary reversible/quantum comparators
- Logical reversibility of computation
- Minimization of Quaternary Galois Field Sum of Products Expression for Multi-Output Quaternary Logic Function Using Quaternary Galois Field Decision Diagram
- GF(4) Based Synthesis of Quaternary Reversible/Quantum Logic Circuits
- Synthesis of Reversible Circuits from a Subset of Muthukrishnan-Stroud Quantum Realizable Multi-Valued Gates
- Quantum Realization of Multiple-Valued Feynman and Toffoli Gates without Ancilla Input
- Reversible Realization of Quaternary Decoder, Multiplexer, and Demultiplexer Circuits
- Terary GFSOP Minimization Using Kronecker Decision Diagrams and Their Synthesis with Quantum Cascades
- Synthesis of Quantum Multiple-Valued Circuits
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