Generating interlocked instruction pipelines from specifications of instruction sets
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Summary
Methods to generate pipelined processors from a bare instruction set specification in ViDL, yielding processors with clock frequencies of 260 - 680MHz for 2 - 7 stage pipelines is presented.
- Type
- article
- Published
- 2012-10-07
- Cited by
- 2
- References
- 21
- OpenAlex
- https://openalex.org/W2034779352
- Semantic Scholar
- https://api.semanticscholar.org/CorpusID:7881841
Keywords
Computer science, Instruction set, Microarchitecture, Compiler, Semantics (computer science)
References
- Designing SOCs with Configured Cores: Unleashing the Tensilica Xtensa and Diamond Cores (Systems on Silicon)
- Computer Architecture, Fifth Edition: A Quantitative Approach
- Programming language design concepts
- Computer Architecture: A Quantitative Approach
- Computer systems design and architecture
- PEAS-III: an ASIP design environment
- EXPRESSION: a language for architecture exploration through compiler/simulator retargetability
- Hardware/software instruction set configurability for system-on-chip processors
- ViDL: A Versatile ISA Description Language
- High level synthesis from Sim-nML processor models
- Xtensa: A Configurable and Extensible Processor
- An evaluation of CoWare Inc.'s Processor Designer tool suite for the design of embedded processors.
- Generating processors from specifications of instruction sets
- ARM Architecture Reference Manual
- Computer Systems Design and Architecture (2nd Edition)
- Type Analysis on Bitstring Expressions
- nML: A Structural Processor Modeling Language for Retargetable Compilation and ASIP Design
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