Dark silicon and the end of multicore scaling
Explore this paper's citation graph
- Type
- article
- Published
- 2011-06-04
- Cited by
- 2,211
- References
- 30
- Access
- Open access
- OpenAlex
- https://openalex.org/W2006312753
- Semantic Scholar
- https://api.semanticscholar.org/CorpusID:62736408
Keywords
Silicon, Scaling, Multi-core processor, Computer science, Parallel computing
References
- Power Scaling: the Ultimate Obstacle to 1K-Core Chips
- Analyzing CUDA workloads using a detailed GPU simulator
- Design Of Ion-implanted MOSFET's with Very Small Physical Dimensions
- Cramming More Components Onto Integrated Circuits
- The Exascale challenge
- Amdahl's Law in the Multicore Era
- Scaling, Power and the Future of CMOS
- Extending Amdahl's Law for Energy-Efficient Computing in the Many-Core Era
- Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?
- Accelerating critical section execution with asymmetric multi-core architectures
- Corollaries to Amdahl's Law for Energy
- Composable Lightweight Processors
- Energy-performance tradeoffs in processor architecture and circuit design: a marginal cost analysis
- Many-Core vs. Many-Thread Machines: Stay Away From the Valley
- Validity of the single processor approach to achieving large scale computing capabilities
- Accelerating Critical Section Execution with Asymmetric Multicore Architectures
- Conservation cores: reducing the energy of mature computations
- Understanding PARSEC performance on contemporary CMPs
- Debunking the 100X GPU vs. CPU myth: an evaluation of throughput computing on CPU and GPU
- Looking back on the language and hardware revolutions: measured power, performance, and scaling
Cited by
- Towards Power Efficiency on Task-Based, Decoupled Access-Execute Models
- Pi-Ware: An Embedded Hardware Description Language using Dependent Types
- Contech: a shared memory parallel program analysis framework
- Adaptive Distributed Architectures for Future Semiconductor Technologies
- An On-Chip Trainable and the Clock-Less Spiking Neural Network With 1R Memristive Synapses
- Learning-based runtime management of energy-efficient and reliable many-core systems
- High-Level Power Estimation and Optimization of DRAMs
- Real-time Cloud Rendering on the GPU
- Dark Silicon is Sub-Optimal and Avoidable
- Collaborative and Adaptive Mobile Device-resident Service Architectures
- Energy-Efficient Algorithms on Mesh-Connected Systems with Additional Communication Links
- Designing, optimizing, and sustaining heterogeneous chip multiprocessors to systematically exploit dark silicon
- SYNCHRONIZATION-POINT DRIVEN RESOURCE MANAGEMENT IN CHIP MULTIPROCESSORS
- Selective Core Boosting: The Return of the Turbo Button
- Accelerating Similarly Structured Data
- The Implications of Shared Data Synchronization Techniques on Multi-Core Energy Efficiency
- Potentia Est Scientia: Security and Privacy Implications of Energy-Proportional Computing
- Composable Flexible Real-time Packet Scheduling for Networks on-Chip
- Myrmics: A scalable runtime system for global address spaces
- Time and energy modeling of high-performance Level-3 BLAS on x86 architectures
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