Estudo e implementação de somador com detecção de fim de cálculo para circuitos assíncronos
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- Type
- dissertation
- Published
- 2005-01-01
- Cited by
- 0
- References
- 22
- Access
- Open access
- OpenAlex
- https://openalex.org/W1051915
- Semantic Scholar
- https://api.semanticscholar.org/CorpusID:59623438
Keywords
Computer science
References
- Computer arithmetic - algorithms and hardware designs
- Compact 32-bit CMOS adder in multiple-output DCVS logic for self-timed circuits
- Cascode voltage switch logic: A differential CMOS logic family
- Ultrafast compact 32-bit CMOS adders in multiple-output domino logic
- Asynchronous datapaths and the design of an asynchronous adder
- Compact four bit carry look-ahead CMOS adder in multi-output DCVS logic
- Implementation of iterative networks with CMOS differential logic
- Formal design procedures for pass transistor switching circuits
- Addition to "Evaluation of three 32-bit CMOS" adders in DCVS logic for self-timed circuits"
- Design and performance analysis of delay insensitive multi-ring structures
- Design procedures for differential cascode voltage switch circuits
- CMOS circuit design of threshold gates with hysteresis
- Design of submicrometer CMOS differential pass-transistor logic circuits
- NULL Convention Logic/sup TM/: a complete and consistent logic for asynchronous digital circuit synthesis
- Performance of CMOS differential circuits
- Cell designs for self-timed FPGAs
- Optimization of Submicron CMOS Differential Pass-Transistor Logic
- Fast adders using enhanced multiple-output domino logic
- Differential pass-transistor logic partial-product generator for iterative multipliers
- NULL Convention Logic
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