Designing reverse converter for data transmission systems from two-level RNS to BNS

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Summary

The simulation of FPGA reverse conversion to a two-stage RNS using the proposed method and the standard CRT using adders is discussed, their comparison of latency and hardware costs are discussed.

Type
article
Published
2020-10-01
Cited by
1
References
7
Access
Open access

Keywords

Residue number system, Adder, Chinese remainder theorem, Field-programmable gate array, Binary number

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