Designing reverse converter for data transmission systems from two-level RNS to BNS
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Summary
The simulation of FPGA reverse conversion to a two-stage RNS using the proposed method and the standard CRT using adders is discussed, their comparison of latency and hardware costs are discussed.
- Type
- article
- Published
- 2020-10-01
- Cited by
- 1
- References
- 7
- Access
- Open access
- OpenAlex
- https://openalex.org/W3165361020
- Semantic Scholar
- https://api.semanticscholar.org/CorpusID:236843206
Keywords
Residue number system, Adder, Chinese remainder theorem, Field-programmable gate array, Binary number
References
- RNS reverse converters for moduli sets with dynamic ranges of 9n-bit
- Residue Number Systems: Theory and Implementation
- An Efficient Reverse Converter for the Three-Moduli Set ( 2^n+1-1, 2^n, 2^n-1 )
- Increasing of convolutional neural network performance using residue number system
- APD-JFAD: Accurate Prevention and Detection of Jelly Fish Attack in MANET
- Designing forward converters for data transmission systems in two-level RNS
- Application of the residue number system to reduce hardware costs of the convolutional neural network implementation
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