SEFR: A Fast Linear-Time Classifier for Ultra-Low Power Devices
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Summary
This work proposes an ultra-low power binary classifier, SEFR, with linear time complexity, both in the training and the testing phases, and is the first multipurpose algorithm specifically devised for learning on ultra- low power devices.
- Type
- preprint
- Published
- 2020-06-08
- Cited by
- 16
- References
- 31
- Access
- Open access
- OpenAlex
- https://openalex.org/W3033182743
- Semantic Scholar
- https://api.semanticscholar.org/CorpusID:219531117
Keywords
Computer science, Classifier (UML), Power consumption, Ultra low power, Binary classification
References
- Safe Screening Rules for Accelerating Twin Support Vector Machine Classification
- An empirical study of the naive Bayes classifier
- A new definition of neighborhood of a point in multi-dimensional space
- The Complexity of Finding Minimal Voronoi Covers with Applications to Machine Learning
- K-nearest neighbor
- Improving the k-NCN classification rule through heuristic modifications
- Real-time KD-tree construction on graphics hardware
- Spark: Cluster Computing with Working Sets
- XGBoost: A Scalable Tree Boosting System
- Scalable Daily Human Behavioral Pattern Mining from Multivariate Temporal Data
- Federated Learning: Strategies for Improving Communication Efficiency
- A natural language query interface for searching personal information on smartwatches
- Integrating machine learning in embedded sensor systems for Internet-of-Things applications
- GPU-Accelerated Parallel Hierarchical Extreme Learning Machine on Flink for Big Data
- MobileNets: Efficient Convolutional Neural Networks for Mobile Vision Applications
- Resource-efficient Machine Learning in 2 KB RAM for the Internet of Things
- CatBoost: unbiased boosting with categorical features
- ProjectionNet: Learning Efficient On-Device Deep Networks Using Neural Projections
- Accurate frequency-based lexicon generation for opinion mining
- LightGBM: A Highly Efficient Gradient Boosting Decision Tree
Cited by
- Improved Butterfly Optimization Algorithm for Data Placement and Scheduling in Edge Computing Environments
- 11 Years with Wearables
- ML-MCU: A Framework to Train ML Classifiers on MCU-Based IoT Edge Devices
- Train++: An Incremental ML Model Training Algorithm to Create Self-Learning IoT Devices
- Globe2Train: A Framework for Distributed ML Model Training using IoT Devices Across the Globe
- LightDepth: A Resource Efficient Depth Estimation Approach for Dealing with Ground Truth Sparsity via Curriculum Learning
- ODSearch
- Performance Analysis of Machine Learning Algorithm on GD32 Microcontrollers
- TinyProp - Adaptive Sparse Backpropagation for Efficient TinyML On-device Learning
- Analisis Performa Algoritma Machine Learning pada Perangkat Embedded ATmega328P
- Real-time invasive sea lamprey detection using machine learning classifier models on embedded systems
- Advancing On-Device Neural Network Training with TinyPropv2: Dynamic, Sparse, and Efficient Backpropagation
- A novel One-vs-Next approach for multiclass classification
- RockNet: Distributed Learning on Ultra-Low-Power Devices
- FEDZIP: A Compression Framework for Communication-Efficient Federated Learning
- ODSearch: A Fast and Resource Efficient On-device Information Retrieval for Mobile and Wearable Devices
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