Scaling Binarized Neural Networks on Reconfigurable Logic
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Summary
It is shown how padding can be employed on BNNs while still maintaining a 1-bit datapath and high accuracy, and it is believed that a large BNN requiring 1.2 billion operations per frame can classify images at 12 kFPS with 671 μs latency while drawing less than 41 W board power and classifying CIFAR-10 images at 88.7% accuracy.
- Type
- article
- Published
- 2017-01-12
- Cited by
- 60
- References
- 29
- Access
- Open access
- OpenAlex
- https://openalex.org/W2583831344
- Semantic Scholar
- https://api.semanticscholar.org/CorpusID:6915137
Keywords
Computer science, Datapath, Field-programmable gate array, Scalability, Frame rate
References
- High Performance Convolutional Neural Networks for Document Processing
- Very Deep Convolutional Networks for Large-Scale Image Recognition
- CNP: An FPGA-based processor for Convolutional Networks
- Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks
- Going deeper with convolutions
- Gradient-based learning applied to document recognition
- Evaluation of convolutional neural networks for visual recognition
- ImageNet classification with deep convolutional neural networks
- FireCaffe: Near-Linear Acceleration of Deep Neural Network Training on Compute Clusters
- BinaryNet: Training Deep Neural Networks with Weights and Activations Constrained to +1 or -1
- Resiliency of Deep Neural Networks under Quantization
- Bitwise Neural Networks
- Accelerating Deep Convolutional Neural Networks Using Specialized Hardware
- SqueezeNet: AlexNet-level accuracy with 50x fewer parameters and <1MB model size
- Convolutional networks for fast, energy-efficient neuromorphic computing
- Theano: A Python framework for fast computation of mathematical expressions
- YodaNN: An Ultra-Low Power Convolutional Neural Network Accelerator Based on Binary Weights
- Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks
- DoReFa-Net: Training Low Bitwidth Convolutional Neural Networks with Low Bitwidth Gradients
- Ternary neural networks for resource-efficient AI applications
Cited by
- Fixed-point optimization of deep neural networks with adaptive step size retraining
- Deep Reservoir Computing Using Cellular Automata
- Compressing Low Precision Deep Neural Networks Using Sparsity-Induced Regularization in Ternary Networks
- Scaling Neural Network Performance through Customized Hardware Architectures on Reconfigurable Logic
- Accelerating CNN inference on FPGAs: A Survey
- A Customizable Matrix Multiplication Framework for the Intel HARPv2 Xeon+FPGA Platform: A Deep Learning Case Study
- A Survey to Predict the Trend of AI-able Server Evolution in the Cloud
- A Bit-Encoding Based New Data Structure for Time and Memory Efficient Handling of Spike Times in an Electrophysiological Setup
- Deep Learning with Cellular Automaton-Based Reservoir Computing
- Toolflows for Mapping Convolutional Neural Networks on FPGAs
- Multi-precision convolutional neural networks on heterogeneous hardware
- SYQ: Learning Symmetric Quantization for Efficient Deep Neural Networks
- Real-time computer vision in software using custom vector overlays
- Design Flow of Accelerating Hybrid Extremely Low Bit-Width Neural Network in Embedded FPGA
- BinaryEye: A 20 kfps Streaming Camera System on FPGA with Real-Time On-Device Image Recognition Using Binary Neural Networks
- FINN-R
- Bitcoding the brain. Integration and organization of massive parallel neuronal data.
- A survey of FPGA-based accelerators for convolutional neural networks
- Logic Synthesis of Binarized Neural Networks for Efficient Circuit Implementation
- High-Efficiency Convolutional Ternary Neural Networks with Custom Adder Trees and Weight Compression
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