The MasPar MP-1 architecture

Tom Blank · Digest of Papers Compcon Spring '90. Thirty-Fifth IEEE Computer Society International Conference on Intellectual Leverage · 1990

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Type: article
Published: 1990-02-26
Cited by: 337
References: 5
DOI: https://doi.org/10.1109/cmpcon.1990.63648
OpenAlex: https://openalex.org/W2538506363
Semantic Scholar: https://api.semanticscholar.org/CorpusID:25585812

Keywords

Computer science, Computer architecture, SIMD, Compiler, Architecture

References

A VLSI chip set for a massively parallel architectureR. Grondalski — 1987
DAP - A Distributed Array ProcessorS.F. Reddaway — 1973
Design of a Massively Parallel ProcessorBatcher — 1980
The connection machineW. Daniel Hillis — 1985
Efficient scan operators for bit-serial processor arraysCharles M. Fiduccia, R.M. Mattheyses, Richard E. Stearns — 1988
Design of a massively parallel processorKenneth E. Batcher — 1986

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Strategies for the Implementation of Interconnection Network Simulators on Parallel ComputersMichael Jurczyk, Thomas Schwederski, Howard Jay Siegel — 1998
Computers and Thought Award : Challenges of Massive ParallelismHiroaki Kitano — 1993
Scheduling Or-Parallelism in MuseKhayri A. M. Ali, Roland Karlsson — 1991
Designing parallel computers for self organizing mapsTomas Nordström — 1991
The concert system--compiler and runtime support for efficient, fine-grained concurrent object-oriented programsAndrew A. Chien, Vijay Karamcheti, John Plevyak — 1993
Vliw processors: efficiently exploiting instruction level parallelismMichael Flynn, Kevin W. Rudd — 2000
Designing optimal parallel volume rendering algorithmsCraig M. Wittenbrink — 1993
Mixed-Mode Programmable and Scalable Architecture for On-Chip LearningBassem Alhalabi, Magdy Bayoumi, Bassem Maaz — 1999
Challenges of massive parallelismHiroaki Kitano — 1993
MpNoC Design: Modeling and SimulationSimon Duquennoy, Philippe Marquet Samy Meftali, Jean‐Luc Dekeyser — 2006
Experimental Evaluation and Workload Characterization for High-Performance Computer ArchitecturesTarek A. El-Ghazawi — 1995
Probabilistic analysis on mesh network fault toleranceJianer Chen, GaoCai Wang, GaoCai Wang — 2007
A COMPREHENSIVE HDL MODEL OF A LINE ASSOCIATIVE REGISTER BASED ARCHITECTUREMatthew A. Sparks — 2013
Optical interconnections in parallel radar signal processing systemsMagnus Jönsson — 1999
Understanding and Improving High-Performance I/O SubsystemsTarek A. El-Ghazawi, Gideon Frieder, A. James Clark — 1996
Adéquation algorithmes et architectures parallèles pour la reconstruction 3D en tomographie X. (Adequation beetween algorithms and parallel machines for 3D reconstruction on X-Ray Tomography)Camille Laurent — 1996
Memory considerations for high performance SIMD systems with on-chip controlMartin Herbordt, J. Cravy, Calvin Lin — 2003
Common Subexpression InductionHenry G. Dietz — 1992

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