The thrifty barrier: energy-aware synchronization in shared-memory multiprocessors
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- Type
- article
- Published
- 2004-02-14
- Cited by
- 129
- References
- 28
- OpenAlex
- https://openalex.org/W2535431417
- Semantic Scholar
- https://api.semanticscholar.org/CorpusID:5645718
Keywords
Computer science, Leverage (statistics), Parallel computing, Synchronization (alternating current), Multiprocessing
References
- Load balancing and unbalancing for power and performance in cluster-based systems
- Power Aware Computing
- Energy Conservation Policies for Web Servers
- Implications of hierarchical N-body methods for multiprocessor architectures
- Power aware microarchitecture resource scaling
- Integrating adaptive on-chip storage structures for reduced dynamic power
- On evaluating request-distribution schemes for saving energy in server clusters
- Saving energy with architectural and frequency adaptations for multimedia applications
- Power and energy reduction via pipeline balancing
- Positional adaptation of processors: application to energy reduction
- Evaluating synchronization on shared address space multiprocessors: methodology and performance
- JETTY: filtering snoops for reduced energy consumption in SMP servers
- Speculative synchronization: applying thread-level speculation to explicitly parallel applications
- The directory-based cache coherence protocol for the DASH multiprocessor
- Energy-effective issue logic
- An evaluation of memory consistency models for shared-memory systems with ILP processors
- Selective cache ways: on-demand cache resource allocation
- Energy-Efficient Server Clusters
- The SPLASH-2 programs: characterization and methodological considerations
- The SPLASH-2 programs
Cited by
- Power Management for GPU-CPU Heterogeneous Systems
- SYNCHRONIZATION-POINT DRIVEN RESOURCE MANAGEMENT IN CHIP MULTIPROCESSORS
- Energy optimization of representative barrier algorithms
- Cross-Layer Customization for low Power and High Performance Embedded Multi-Core Processors
- Use of wireless sensors to improve robot lifetime for multi-threat containment
- Performance Measurement : Current Perspectives and Future Challenges
- A Hardware Synchronization for Multicore Embedded Systems
- THE CASE FOR HARDWARE OVERPROVISIONED SUPERCOMPUTERS
- Computational sprinting: exceeding sustainable power in thermally constrained systems
- Fair and high performance shared memory resource management
- Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors
- The Need for Power Debugging in the Multi-Core Environment
- An analysis of the energy efficiency of multi-threading on multi-core machines
- Embracing heterogeneity with dynamic core boosting
- Thread-management techniques to maximize efficiency in multicore and simultaneous multithreaded microprocessors
- Adagio: making DVS practical for complex HPC applications
- EEWA: Energy-Efficient Workload-Aware Task Scheduling in Multi-core Architectures
- Efficient inter-core power and thermal balancing for multicore processors
- Investigation on the power efficiency of multi-core and GPU Processing Element in large scale SIMD computation with CUDA
- Callback: Efficient synchronization without invalidation with a directory just for spin-waiting
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