ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars
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- Type
- article
- Published
- 2016-06-01
- Cited by
- 2,019
- References
- 91
- OpenAlex
- https://openalex.org/W2518281301
- Semantic Scholar
- https://api.semanticscholar.org/CorpusID:6329628
Keywords
Computer science, Throughput, Crossbar switch, Memristor, Pipeline (software)
References
- Design and Optimization
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- Exploring the design space of specialized multicore neural processors
- Nonvolatile memristor memory: Device characteristics and design implications
- RENO: A high-efficient reconfigurable neuromorphic computing accelerator design
- Bridging the semantic gap: Emulating biological neuronal behaviors with simple digital neurons
- Design of silicon brains in the nano-CMOS era: Spiking neurons, learning synapses and neural architecture optimization
- CNP: An FPGA-based processor for Convolutional Networks
- Deep Learning Face Representation from Predicting 10,000 Classes
- An analog neural network processor with programmable topology
- PuDianNao: A Polyvalent Machine Learning Accelerator
- Energy efficient perceptron pattern recognition using segmented memristor crossbar arrays
- A 10-nW 12-bit accurate analog storage cell with 10-aA leakage
- Q100: the architecture and design of a database processing unit
- Leveraging the error resilience of machine-learning applications for designing highly energy efficient accelerators
- Overcoming the challenges of crossbar resistive memory architectures
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- PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory
- Minerva: Enabling Low-Power, Highly-Accurate Deep Neural Network Accelerators
- Fathom: reference workloads for modern deep learning methods
- Reconfigurable in-memory computing with resistive memory crossbar
- The Processing Using Memory Paradigm: In-DRAM Bulk Copy, Initialization, Bitwise AND and OR
- Sparsely-Connected Neural Networks: Towards Efficient VLSI Implementation of Deep Neural Networks
- Accelerating Discrete Fourier Transforms with dot-product engine
- Buddy-RAM: Improving the Performance and Efficiency of Bulk Bitwise Operations Using DRAM
- Hardware for machine learning: Challenges and opportunities
- An FPGA-Based Hardware Accelerator for Traffic Sign Detection
- YodaNN: An Architecture for Ultralow Power Binary-Weight CNN Acceleration
- Binary convolutional neural network on RRAM
- IMEC: A Fully Morphable In-Memory Computing Fabric Enabled by Resistive Crossbar
- RESPARC: A reconfigurable and energy-efficient architecture with Memristive Crossbars for deep Spiking Neural Networks
- DLPlib: A Library for Deep Learning Processor
- Recent Technology Advances of Emerging Memories
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