Resource allocation and binding approach for low leakage power

Keywords

Idle, CMOS, Computer science, Transistor, Leakage (economics)

References

• High-Level Power Analysis and OptimizationAnand Raghunathan, Niraj K. Jha, Sujit Dey — 1997
• Architectural approaches to reduce leakage energy in cachesS.H. Tadas, Chaitali Chakrabarti — 2002
• Dual-threshold voltage techniques for low-power digital circuitsJames Kao, Anantha P. Chandrakasan — 2000
• Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacksZhanping Chen, Mark C. Johnson, Liqiong Wei — 1998
• DRG-cache: a data retention gated-ground cache for low powerAmit Agarwal, Hai Li, Kaushik Roy — 2002
• Leakage power analysis and reduction during behavioral synthesisK.S. Khouri, Niraj K. Jha — 2002
• Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memoriesMichael D. Powell, Se-Hyun Yang, Babak Falsafi — 2000
• Behavioral synthesis of datapaths with low leakage powerC. Gopalakrishnan, Srinivas Katkoori — 2002
• Facet: A Procedure for the Automated Synthesis of Digital SystemsChia-Jeng Tseng, Daniel P. Siewiorek — 1983
• Leakage power reduction in low-voltage CMOS designsKaushik Roy — 1998
• A gate-level leakage power reduction method for ultra-low-power CMOS circuitsJonathan Paul Halter, Farid N. Najm — 1997
• Estimation of standby leakage power in CMOS circuit considering accurate modeling of transistor stacksZhanping Chen, Mark C. Johnson, Liqiong Wei — 1998
• Facet: A Procedure for the Automated Synthesis of Digital SystemsChia-Jeng Tseng, D.P. Siewiorek — 1983

Cited by

• Power-Management Scheduling for Peak Power MinimizationShih-Hsu Huang, Chun-Hua Cheng — 2008
• Behavioral and RT-Level Estimation and Optimization of Crosstalk in VLSI ASICsS. Gupta, Srinivas Katkoori — 2004
• Leakage power driven behavioral synthesis of pipelined asicsR. Gopalan — 2005
• Variability-aware low-power techniques for nanoscale mixed-signal circuits.Dhruva Ghai — 2009
• Leakage power driven behavioral synthesis of pipelined datapathsR. Gopalan, C. Gopalakrishnan, Srinivas Katkoori — 2005
• Device circuit co‐design to reduce gate leakage current in VLSI logic circuits in nano regimeAshwani K. Rana — 2016
• Power optimization in data-path scheduling and binding with multiple supply voltages and threshold voltages by simulated annealingJianfeng Huang, Jinian Bian, Z. H. Liu — 2005
• HLS-dv: A High-Level Synthesis Framework for Dual-Vdd ArchitecturesInsup Shin, Seungwhun Paik, Dongwan Shin — 2012
• ILP based leakage optimization during nano-CMOS RTL synthesis: A DOXCMOS Versus DTCMOS perspectiveSaraju P. Mohanty, Bijaya Ketan Panigrahi — 2009
• LECTOR: a technique for leakage reduction in CMOS circuitsNarender Hanchate, N. Ranganathan — 2004
• Standby leakage reduction in nanoscale CMOS VLSI circuitsJyoti Deshmukh, Kavita Khare — 2010
• Tabu search based behavioural synthesis of low leakage datapathsC. Gopalakrishnan, Srinivas Katkoori — 2004
• Exploiting temporal idleness to reduce leakage power in programmable architecturesR.P. Bharadwaj, R. Konar, Poras T. Balsara — 2005
• Reducing Functional Unit Power Consumption and its Variation Using Leakage SensorsAviral Shrivastava, Deepa Kannan, Sarvesh Bhardwaj — 2010
• High Level Synthesis Of An Image Processing Algorithm For Cancer DetectionAnuleka Bilhanan — 2004
• Timed Input Pattern Generation for an Accurate Delay Calculation Under Multiple Input SwitchingSeung Hoon Choi, Kunhyuk Kang, Florentin Dartu — 2010
• A Framework for Power-Gating Functional Units in Embedded MicroprocessorsSoumyaroop Roy, N. Ranganathan, Srinivas Katkoori — 2009
• Reduction of Power Dissipation in Logic CircuitsSreenivasa Rao Ijjada, Author B.Ramparamesh, Vallu Visrutatma Rao — 2011
• Hardware-Based Load Balancing for Massive Multicore Architectures Implementing Power GatingEnric Musoll — 2010
• Power Management Aware Low Leakage Behavioural SynthesisSven Rosinger, Kiril Schröder, Wolfgang Nebel — 2009

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