Cell processor low-power design methodology
Explore this paper's citation graph
- Type
- article
- Published
- 2005-11-01
- Cited by
- 20
- References
- 7
- OpenAlex
- https://openalex.org/W2093621020
- Semantic Scholar
- https://api.semanticscholar.org/CorpusID:1590879
Keywords
Computer science, Very-large-scale integration, Power (physics), Power optimization, Power analysis
References
- The clock distribution of the Power4 microprocessor
- The design and implementation of a first-generation CELL processor
- Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors
- Unified architecture level energy-efficiency metric
- A clock distribution network for microprocessors
- CPAM: a common power analysis methodology for high-performance VLSI design
- Power modeling for high-level power estimation
- The clock distribution of the Power4 microprocessor
Cited by
- Constraint based methods for allocation and scheduling of periodic applications
- Power-optimal RTL arithmetic unit soft-macro selection strategy for leakage-sensitive technologies
- Power signal processing: a new perspective for power analysis and optimization
- Design and implementation of soft-edge flip-flops for x86-64 AMD microprocessor modules
- Low Power and Energy Efficient Asynchronous Design
- Circuit Design Techniques for a First-Generation Cell Broadband Engine Processor
- Performance Evaluation of Multi-core Processors with Varied Interconnect Networks
- Multicore Processors - A Necessity
- Key Establishment in Multi-core Parallel Systems
- Fusion: Design tradeoffs in coherent cache hierarchies for accelerators
- Analysing the Performance of Multi-core Architecture
- IEEE MICRO 2005 ANNUAL INDEX, VOL. 25
- Constraint based methods for allocation and scheduling of periodic applications
- Design and implementation of tool-chain framework to support OpenMP single source compilation on cell platform
- A constraint programming scheduling solver for the MPOpt programming environment
- Chainsaw: Von-neumann accelerators to leverage fused instruction chains
- Specialized Macro-Instructions for Von-Neumann Accelerators
- Generalized methods for application specific hardware specialization
- Multi-core Processors - A Necessity
- Fusion
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