A Layer Model for Systematically Designing Dynamically Reconfigurable Systems
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- Type
- article
- Published
- 2006-08-01
- Cited by
- 8
- References
- 9
- OpenAlex
- https://openalex.org/W2039520903
- Semantic Scholar
- https://api.semanticscholar.org/CorpusID:15918282
Keywords
Control reconfiguration, Reusability, Field-programmable gate array, Computer science, Embedded system
References
- Real-Time Dynamically Run-Time Reconfiguration for Power-/Cost-optimized Virtex FPGA Realizations
- A Prototyping Platform for Dynamically Reconfigurable System on Chip Designs
- PARBIT: A Tool to Transform Bitfiles to Implement Partial Reconfiguration of Field Programmable Gate Arrays (FPGAs)
- Context saving and restoring for multitasking in reconfigurable systems
- Task placement for heterogeneous reconfigurable architectures
- REPLICA: a bitstream manipulation filter for module relocation in partial reconfigurable systems
- The Erlangen Slot Machine: a highly flexible FPGA-based reconfigurable platform
- Specification for the : WISHBONE System-On-Chip ( SoC ) Interconnection Architecture for Portable IP Cores
- Modular partial reconfigurable in Virtex FPGAs
Cited by
- A Case Study: Task Scheduling Methodologies for High Speed Computing Systems
- Model-based platform-specific co-design methodology for dynamically partially reconfigurable systems with hardware virtualization and preemption
- ATtACk - A methodology for realizing partially reconfigurable FPGA systems
- Bitstreams Repository Hierarchy for FPGA Partially Reconfigurable Systems
- A NOVEL METHODOLOGY FOR TASK DISTRIBUTION IN HETEROGENEOUS RECONFIGURABLE COMPUTING SYSTEM
- IN HETEROGENEOUS RECONFIGURABLE COMPUTING SYSTEM
- Methods for the Design and Development
- Survey on High Speed Computing System Architectures
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