WiT: Optimal Wiring Topology for Electromigration Avoidance
Explore this paper's citation graph
- Type
- article
- Published
- 2012-04-01
- Cited by
- 22
- References
- 28
- OpenAlex
- https://openalex.org/W1979787852
- Semantic Scholar
- https://api.semanticscholar.org/CorpusID:25687845
Keywords
Heuristics, Electromigration, Topology (electrical circuits), Network topology, Greedy algorithm
References
- Introduction to Algorithms, third edition
- Current-driven wire planning for electromigration avoidance in analog circuits
- Electromigration study of power-gated grids
- A model for conductor failure considering diffusion concurrently with electromigration resulting in a current exponent of 2
- Electromigration—A brief survey and some recent results
- Obstacle-avoiding rectilinear Steiner minimum tree construction: An optimal approach
- Optimal wiring topology for electromigration avoidance considering multiple layers and obstacles
- Berkeley reliability tools-BERT
- introduction to electromigration-aware physical design
- Finding minimum-cost circulations by canceling negative cycles
- Early-stage determination of current-density criticality in interconnects
- New algorithms for the rectilinear Steiner tree problem
- Single step current driven routing of multiterminal signal nets for analog applications
- Electromigration reliability comparison of Cu and Al interconnects
- Static electromigration analysis for on-chip signal interconnects
- FOARS: FLUTE Based Obstacle-Avoiding Rectilinear Steiner Tree Construction
- A current driven routing and verification methodology for analog applications
- An electromigration and thermal model of power wires for a priori high-level reliability prediction
- Self-consistent solutions for allowed interconnect current density. II. Application to design guidelines
- Electromigration-aware rectilinear Steiner tree construction for analog circuits
Cited by
- Prévision des effets de vieillissement par électromigration dans les circuits intégrés CMOS en nœuds technologiques submicroniques. (Forecasting the effects of aging by electromigration in the circuits integrated CMOS submicron technology nodes)
- A prognostic circuit for time-dependent dielectric breakdown failure of MOSFET
- Electromigration-aware analog Router with multilayer multiport terminal structures
- Power grid redundant path contribution in system on chip (SoC) robustness against electromigration
- Design of prognostic circuit for electromigration failure of integrated circuit
- Electromigration- and obstacle-avoiding routing tree construction
- Redundancy method to assess electromigration lifetime in power Grid design
- Methodology for electromigration signoff in the presence of adaptive voltage scaling
- Recent research development and new challenges in analog layout synthesis
- Design for manufacturability and reliability in extreme-scaling VLSI
- Quantum circuit design for objective function maximization in gate-model quantum computers
- Electromigration- and Parasitic-Aware ILP-Based Analog Router
- Entanglement concentration service for the quantum Internet
- Tackling Signal Electromigration with Learning-Based Detection and Multistage Mitigation
- IR-aware Power Net Routing for Multi-Voltage Mixed-Signal Design
- Avoidance vs. repair: New approaches to increasing electromigration robustness in VLSI routing
- Design of a 4.2-to-5.1 GHz Ultralow-Power Complementary Class-B/C Hybrid-Mode VCO in 65-nm CMOS Fully Supported by EDA Tools
- Electromigration-aware and IR-Drop avoidance routing in analog multiport terminal structures
- Hierarchical Analog and Mixed-Signal Circuit Placement Considering System Signal Flow
- Study of electromigration in integrated circuits at design level
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