Design and evaluation of basic standard encryption algorithm modules using nanosized complementary metal–oxide–semiconductor–molecular circuits
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Summary
It is observed that CMOL provides considerable improvement over implementation with regular CMOS architecture even with a 20% defect rate.
- Type
- article
- Published
- 2006-01-14
- Cited by
- 178
- References
- 24
- Access
- Open access
- OpenAlex
- https://openalex.org/W1976484620
- Semantic Scholar
- https://api.semanticscholar.org/CorpusID:109898814
Keywords
Advanced Encryption Standard, Encryption, CMOS, Materials science, Key (lock)
References
- Nano and Giga Challenges in Microelectronics
- The Design of Rijndael
- Future challenges in VLSI system design
- New Frontiers: Self-Assembly and Nanoelectronics
- Masking the energy behaviour of encryption algorithms
- Prospects for terabit-scale nanoelectronic memories
- Report on the Development of the Advanced Encryption Standard (AES)
- Architectures and VLSI Implementations of the AES-Proposal Rijndael
- CMOS/nano co-design for crossbar-based molecular electronic systems
- CMOL FPGA: a reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices
- Implementation approaches for the Advanced Encryption Standard algorithm
- Fabrication, assembly, and characterization of molecular electronic components
- High-speed VLSI architectures for the AES algorithm
- Differential power analysis, advances in cryptology-CRYPTO'99
- Masking the Energy Behavior of Encryption Algorithms
- An Optimized S-Box Circuit Architecture for Low Power AES Design
- Data Encryption Standard (DES)
- Two Methods of Rijndael Implementation in Reconfigurable Hardware
- Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems
- Architectural Optimization for a 1.82Gbits/sec VLSI Implementation of the AES Rijndael Algorithm
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