Logic synthesis and verification algorithms
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Summary
Logic Synthesis and Verification Algorithms blends mathematical foundations and algorithmic developments with circuit design issues to establish optimal design principles.
- Type
- book
- Published
- 1996-06-30
- Cited by
- 527
- References
- 0
- Access
- Open access
- OpenAlex
- https://openalex.org/W1505590927
- Semantic Scholar
- https://api.semanticscholar.org/CorpusID:5778499
Keywords
Computer science, High-level verification, Automation, Intelligent verification, Very-large-scale integration
References
No references recorded for this paper.
Cited by
- Design Space Re-Engineering for Power Minimization in Modern Embedded Systems
- Automated synthesis and optimization of multilevel logic circuits.
- Digital design automation
- Algorithms for Satisfiability in Combinational Circuits Based on Backtrack Search and Recursive Learning
- Binary decision diagrams in theory and practice
- Efficient Gate and Input Ordering for Circuit-to-BDD Conversion
- Boolean reasoning for digital circuits in presence of unknown values: application to test automation
- Implicit Simulation of FNC Algorithms
- Analyzing Infeasible Constraint Systems
- All Around Logic Synthesis
- A Graph Approach to Two-Level Logic Minimization
- Low Power ASIC Design Using Voltage Scaling at the Logic Level
- ZBDD-Based Backtrack Search SAT Solver
- Testability of SPP Three-Level Logic Networks
- Behavioural synthesis of analogue integrated circuits
- A combined gate replacement and input vector control approach for leakage current reduction
- A novel application of rough set theory for reliable two ways reduction of load data set of a power system
- Hardware Project Management - What we Can Learn from the Software Development Process for Hardware Design?
- BOOM-a heuristic Boolean minimizer
- Anytime algorithms for ROBDD symmetry detection and approximation
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