Parallel H.264 Decoding Strategies for Cell Broadband Engine
Explore this paper's citation graph
Summary
This work implements and compares two parallel H.264 decoders on the Cell architecture and concludes that in order to fully leverage the performance of future many-cores, a centralized master should be avoided and the mapping of tasks to cores should be predictable inorder to be able to hide the memory latency.
- Type
- article
- Published
- 2010-02-05
- Cited by
- 3
- References
- 42
- Access
- Open access
- OpenAlex
- https://openalex.org/W70091612
- Semantic Scholar
- https://api.semanticscholar.org/CorpusID:59830684
Keywords
Computer science, Scalability, Parallel computing, Exploit, Distributed computing
References
- Performance improvement of the H.264/AVC deblocking filter using SIMD instructions
- Hierarchical Parallelization of an H.264/AVC Video Encoder
- The design and implementation of a first-generation CELL processor
- Implementation of H.264 decoder on general-purpose processors with media instructions
- Analysis and Parallelization of H.264 decoder on Cell Broadband Engine Architecture
- Development of MPEG standards for 3D and free viewpoint video
- Efficient mapping of the H.264 encoding algorithm onto multiprocessor DSPs
- Cell Multiprocessor Communication Network: Built for Speed
- Cell Broadband Engine Architecture and its first implementation - A performance view
- Mapping of H.264 decoding on a multiprocessor architecture
- The synergy between non-blocking synchronization and operating system structure
- A performance characterization of high definition digital video decoding using H.264/AVC
- Scalability of Macroblock-level Parallelism for H.264 Decoding
- Analysis of video filtering on the cell processor
- Slice-balancing H.264 video encoding for improved scalability of multicore decoding
- Generalized B pictures and the draft H.264/AVC video-compression standard
- Parallel Scalability of Video Decoders
- Overview of the H.264/AVC video coding standard
- Specialization of the Cell SPE for Media Applications
- HD-VideoBench. A Benchmark for Evaluating High Definition Digital Video Applications
Cited by
Related papers
- Evaluation of parallel H.264 decoding strategies for the Cell Broadband Engine
- Parallel architectures for processing high speed network signaling protocols
- GOP-level parallelization of the H.264 decoder without a start-code scanner
- Two-Level Main Memory Co-Design: Multi-threaded Algorithmic Primitives, Analysis, and Simulation
- Slice-balancing H.264 video encoding for improved scalability of multicore decoding
- Improving Latency Tolerance of Multithreading through Decoupling
- Latency hiding by redundant processing: a technique for grid-enabled, iterative, synchronous parallel programs
- Decoupled vector architectures
- SCALABLE FRAMEWORK WITH IDENTICAL MEMORY DIES TO ACHIEVE HIGH-CLOCK FREQUENCY