VLSI Design of a neurohardware processor implementing the Kohonen Neural Network algorithm

Keywords

Field-programmable gate array, Very-large-scale integration, VHDL, Computer science, Artificial neural network

References

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• Fundamentals Of Neural NetworksLaurene V. Fausett — 1994
• Hardware-friendly learning algorithms for neural networks: an overviewPerry D. Moerland, Emile Fiesler — 1996
• Self-Organizing MapsTeuvo Kohonen — 1995
• Phonetic typewriter for Finnish and JapaneseTeuvo Kohonen, K. Torkkola, Makoto Shozakai — 1988
• A low-cost neuroprocessor board for emulating the SOFM neural modelB. Martín-del-Brío, N. Medrano, Sergio Hernández-Sánchez — 1998
• THE USE OF MULTIPLE MEASUREMENTS IN TAXONOMIC PROBLEMSRonald Aylmer Fisher — 1936
• Computer Systems Organization and ArchitectureJohn Carpinelli — 2000
• UCI Repository of machine learning databasesCatherine Blake — 1998
• The 'neural' phonetic typewriterTeuvo Kohonen — 1988
• Hardware synthesis for neural networks from a behavioral description with VHDLHeike Speckmann, P. Thole, Wolfgang Rosenstiel — 1993
• Logic synthesis speeds ASIC designAart J. de Geus — 1989

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