Package-Level Interconnect Design for Optimum Electrical Performance

Keywords

Motherboard, Power integrity, Signal integrity, Computer science, Interconnection

References

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• Introduction to electromagnetic compatibility2006

Cited by

• Development of Modeling, Simulation and Measurement Methodologies for Signal Integrity Analysis of High-Speed Packaging InterconnectsLin Zhu — 2006
• Modeling of power distribution networks with retardation using the transmission matrix methodTakashi Watanabe, K. Srinivasan, Hideki Asai — 2004
• Solution space analysis of interconnects for low voltage differential signaling (LVDS) applicationsSeungyoung Ahn, A.C.W. Lu, Wei Fan — 2001
• Challenges of small form factor 0402 and 0201 die side capacitor assembly process on high density interconnect flip chip substrateC.C. Loke, Chon-wa Cheong, Hun-Song Goh — 2004
• Physical layout automation for system-on-packagesRamprasad Ravichandran, Jacob Rajkumar Minz, Mohit Pathak — 2004
• Current demand balancing: a technique for minimization of current surge in high performance clock-gated microprocessorsYiran Chen, Kaushik Roy, Cheng‐Kok Koh — 2005
• Applications of a 3-D field solver for on-chip and package microstrip interconnection designWoonghwan Ryu, A.L.C. Wai, Fan Wei — 2000
• Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessorsYiran Chen, Kaushik Roy, Cheng‐Kok Koh — 2003
• Analysis and optimization of power gridsSachin S. Sapatnekar, Huaizhi Su — 2003
• Modeling of power distribution networks with signal lines for SPICE simulatorsTakashi Watanabe, Hideki Asai — 2005
• Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessorYiran Chen, Kaushik Roy, Cheng‐Kok Koh — 2004
• CPU Package Design Optimization for Performance Improvement and Package Cost reductionHowe Yin Loo, Boon Howe Oh, Poh Tat Oh — 2006
• Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessorsYiran Chen, K. Roy, Cheng‐Kok Koh — 2003
• Bypassing, Decoupling, and Power DistributionJ. Barnes — 2004
• A Complete Bibliography of Publications in the Intel Technology JournalN. H. Beebe — 2006

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